Discussion in 'General Technical Questions and Answers' started by KN4LGM, Sep 14, 2020.
I would like to add a GPS reference to my 7300. Has anyone done this something similar?
I have an IC-7300... I've yet to feel it's not stable. Not even remotely.
What issues are you having exactly? Seems "rock solid" on my 7300
If yours isn't stable, I'd be looking at things like power supply issues....
I am interested in the ARRL FMTs, no I have not noticed any wobble but I would like to add it purely for the FMTs. Also, the 9300(and/or 9700) has a 10 Mhz input so I thought it might be possible on the 7300.
OH! Well that is most assuredly a higher standard! I get it now.
The FMT's are no slouch - I used to think they were sort of "relegated to history" but I know it's still very much a big thing.
Good luck in your quest - I'd be curious how the GPS would be injected etc. - assuming USB / virtual serial port?
I'll be watching... cool stuff.
Typically you phase lock a quartz crystal standard to GPS.
Most of this was done years ago so you may need archive.org to track down archives of old web pages.
I know where to buy a GPSDO, what I do not know is how to connect it to my IC 7300. Cool article though!
not grasping this...?
I haven't heard of anyone doing this, probably because its not necessary or worth the effort.
I check my 7300 against my GPSDO every now and then.
Last time, it was +7Hz at 70MHz so an insignificant error as the frequency is lowered.
Doable? Possibly. Worth it? I doubt.
IC-7300 sports a Murata XTCHH oscillator for the FPGA, with +-1 PPM stability. After a initial calibration / frequency alignment in lab, the equipment should be rock stable in HF bands. As @G0GSR mentioned above, that would translate to +- 7 Hz deviation in the worst-case, highest band - 70 MHz band. If you're a 20 meter use? That translates to +- 1.4 Hz deviation.
The tuning (blue arrow) is performed inside the FPGA:
The FPGA is fed by a 41.344 MHz clock rate: (click to enlarge)
So, you would have to essentially have your GPSDO output this clock rate, yank off the existing clock, properly buffer and then feed it to the FPGA.
Remember, if you lose sync/clock, it will probably cause a number of other problems of the radio, as the FPGA controls a number of functions on the radio.
Again; worth it? I doubt it.
The person who won the last FTM was only of by a 100th of a hz off, that is why I want to do it. However, I see what difficulties would come with replacing the existing clock, thanks.