If the validity of the VCCS model for the JFET is accepted (based on the successful comparison for neg R with the real JFET circuit in post #38) I can have an initial stab at showing what would happen if this circuit was modded to have the gate floated on three 200pF caps. Because this is a VCCS model I don't have to add a bias return choke across this network. So don't worry if you spot this isn't present. The top circuit in the simulation below has had this network added at the equivalent of the gate. So it now has three 200pF caps and I've added an extra 12nH inductance per capacitor. So one might think this would be a disaster for stability compared to a direct grounding as in the circuit below it. But look at the prediction for negative resistance. Below 100MHz the floated circuit is much better. This is the dark brown trace. Above 100MHz it is slightly worse. If the caps are reduced in size to 115pF then the floated circuit is better up to about 135MHz. Now this is a JFET model and it isn't the model for a 500Z tube so don't draw too many conclusions yet. But at least this is a first step towards answering the main thread question. It looks like floating the grids may help to (significantly) minimise negative resistance at the lower end of the VHF band. This is the region where the suppressor can't help as much. The suppressor will typically get better with increasing frequency (up to a point). The suppressorZ plot below shows that the ESR of the suppressor drops down to just 15R at 60MHz. So it is not able to protect against negative resistance as well down here. But by floating the grids the tube will produce less negative resistance here. So this all helps to broaded the protection against instability. What you really want on the thread is one of the original designers of these amplifiers. They may agree with me or they may have other thoughts as to why the grids were floated like this.