The sig gen in the plot above is a Marconi 2019A (i.e. synthesised and achieves quite low phase noise at 5MHz due to the use of successive divider networks after one of its V/UHF VCOs)
It's a nicely written article but I do have one very minor comment about the WA1FFL circuit and that is the choice of buffer amplifier. Maybe I've misread something in the various specs but if the WA1FFL board puts out +4dBm into 50R and the buffer has 14dB gain then with its noise performance I would have thought it would slightly degrade the potential noise floor at wide offsets.
Eg the datasheet for the raw DDS implies it can achieve -155dBc/Hz noise floor at 9MHz Fout and 400MHz Fclk. At +4dBm output power this is -151dBm/Hz. If the buffer has ballpark 14dB noise figure and 14dB gain then I'd expect it (alone) to churn out a noise foor at -146dBm/Hz.
Maybe swapping to a lower noise buffer could deliver a slightly better oscillator noise floor? It's not that the current level of performance is poor by any means, it's just it might be possible to claw a bit more performance with a revised buffer amplifier?
When you consider that a very well designed old school analogue VFO can deliver -160dBc/Hz noise floor then it seems a shame to compromise the DDS module performance even slightly?
The sig gen in the plot above is a Marconi 2019A (i.e. synthesised and achieves quite low phase noise at 5MHz due to the use of successive divider networks after one of its V/UHF VCOs)
It's a nicely written article but I do have one very minor comment about the WA1FFL circuit and that is the choice of buffer amplifier. Maybe I've misread something in the various specs but if the WA1FFL board puts out +4dBm into 50R and the buffer has 14dB gain then with its noise performance I would have thought it would slightly degrade the potential noise floor at wide offsets.
Eg the datasheet for the raw DDS implies it can achieve -155dBc/Hz noise floor at 9MHz Fout and 400MHz Fclk. At +4dBm output power this is -151dBm/Hz. If the buffer has ballpark 14dB noise figure and 14dB gain then I'd expect it (alone) to churn out a noise foor at -146dBm/Hz.
Maybe swapping to a lower noise buffer could deliver a slightly better oscillator noise floor? It's not that the current level of performance is poor by any means, it's just it might be possible to claw a bit more performance with a revised buffer amplifier?
When you consider that a very well designed old school analogue VFO can deliver -160dBc/Hz noise floor then it seems a shame to compromise the DDS module performance slightly?
Nice.
To make measurements like that you would need a lead lined room. I have only had a need to measure with a noise floor that low a few times, but it does mater. Maybe you have one ?
Great work. Thanks for sharing. That is good stuff.
73
"Books tell how it should be, Experience tells how it really is..."
73 DE KA9JLM Don
When you consider that a very well designed old school analogue VFO can deliver -160dBc/Hz noise floor then it seems a shame to compromise the DDS module performance even slightly?
I would guess that device was picked because of the application (=<30MHz). The gain flatness of the AD8005N is 0.1dB up to 30MHz. Maybe he was looking at that more than the noise figure, when it is already pretty darn good, but I'm only guessing by looking at the datasheet. There may be other/better devices to use by now anyway. This was designed a few years back I think.
There is another solution that preserves the essence of the BA rigs and that is the Cumbria Designs X-Lock. This is a PIC based Huff&Puff. I have used it on an RME receiver and more recently on my Hallicrafters FPM- 300 MK II. It keeps the VFO within +/- 10Hz and also recognizes XIT/RIT and stores the frequency split.
I have also used the N3ZI DDS VFO in a station accessory I made for my Cubic 103: http://www.parelectronics.com/par-homebrew-projects.php
photos 12 and 13. I increased the clock speed so that it was usable up through 10M.
But again, the X-lock is a teriffic little board, easy to build install and get working.
I've just had a quick play with the AD9850 Eval board with the inbuilt 125MHz clock oscillator. I looked at the 5 to 5.5MHz range on my rather old (but still pretty decent) Advantest spectrum analyser.
The results initially look quite good with a basic setup on the analyser. But once the DDS is tuned in small increments it is quite easy to find frequencies with -73dBc spurs and LOTS of spurs in the -80 to -90dBc range across this 500kHz segment. Eg over a dozen at a time.
I measured very similar performance to that on an AD9850 DDS I made up to fit in the external VFO of my Ten-Tec Corsair II.
However, it has surprised me how seldom those spurs actually seem to cause a problem in practice - maybe because most of them shift frequency rapidly with just slight shifts of the carrier tuning.
I was also pleasantly surprised to find the AD9850 close-in noise is actually better than that of the free-running PTO in the Corsair. I injected a -10dBm signal and moved it slowly away from the Rx passband whilst switching between the internal PTO and the AD9850 external VFO; there was noticeably less noise on the external VFO.
Yes, the phase noise is really good when I look on my analyser here. However, my analyser isn't really the right tool for measuring the true potential of these devices wrt phase noise.
At work we have an E5052A analyser that is simply fabulous for rapidly measuring phase noise down to around -160dBc/Hz. I'll maybe bring in the 9850 and 9954 boards and put them on it. However I think it only goes down to 10MHz Fin so thats's not ideal for VFO testing...
However, I did get the AD9954 board running OK and did a few quick tests here at home.
The 5.2MHz Fout performance when externally clocked at 400MHz is very impressive. Basically it is very difficult to find any spurious displayed on my analyser on 500kHz spans. I'm looking down to around -95 to -100dBc using narrower RBW and narrower spans and it still looks good. At least 20dB better than the 9850? There may well be some spurious hiding in there at certain frequencies within 5 to 5.5MHz but I think I'd need the works E5052A analyser to find them efficiently. Basically, I didn't spend much time looking and simply left it sweeping slowly whilst I looked for any spurious popping up.
However, things aren't so hot on wideband plots if I turn up the Fout to >100MHz. Performance is a bit more ordinary with unslightly spurious at -55dBc typical on a wide span of 100MHz. This is very similar to the performance plots in the datasheet. However, this isn't a worry for VFO use if the VFO frequency is down at a few MHz.
The other thing is I don't have an ideal 400MHz Fclk and I'm using a Marconi 2024 to provide this. But the phase noise from the 9954 at 5MHz Fout still looks amazingly good.
But what is definitely NOT good is what happens to the broadband phase noise if the internal multiplier is enabled.
Eg if I feed in a low noise OCXO at 10MHz http://www.quintenz.de/pdf/xo/QO2736.pdf and multiply x20 to get a 200MHz Fclk the far out phase noise degrades to unacceptable levels if you wanted to generate a highish VFO frequency eg 40MHz.
I get a flat -122dBc/Hz phase noise on the 40MHz signal to offsets over 1MHz from the carrier. This would NOT be good performance for a receiver or a transmitter VFO. Eg if you wanted a high side LO for a 10m radio with a 10.7MHz first IF. it's actually pretty dreadful because of the multiplier. The degradation in noise due to multiplication is a lot worse than the 20log N ratio expected.
If I turn down Fout to 20MHz (Fclk = 200MHz) the phase noise is a bit better but still far from good.
So I would definitely avoid using the multiplier on high multiplication values if low phase noise is desired. I can post up plots of this but the datasheet already hints at how poor the internal multiplier is at high multiplier ratios.
Originally Posted by G0HZU
