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frequency divider

Discussion in 'Homebrew and Kit Projects' started by KB1LQC, Jul 19, 2008.

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  1. KB1LQC

    KB1LQC Guest

    I am building a frequency divider based on the 74HC74 designs (used in the softrock 40 for example) . However I only have 74LS74's at my disposal. I built the circuit the same way as the 74HC74's are built (I am only testing at first with one flip-flop... if I see a frequency thats half... I know its working hihi). The only difference I can see between the 74HC74 and 74LS74 is that the HC has set and reset while the LS has preselect and clear... however, with the set and reset high and the preselect and clear also high, the function table looks the same? I am still gettting my original frequency at the output of 28.236 MHz! Function-wise it checks out... the frequency should be divided by two. I should note that I am not use a prescalar or any circuit to square off the sine wave from the oscillator but was hoping that the divider would still work (with the rising edges) and I believe it should be fine... but either I am doing something wrong or I am completely missing something here! (have a feeling I am going to be laughing at myself with this one!)
     
  2. AB8RO

    AB8RO Ham Member QRZ Page

    The function tables are the same. However, you are exceeding the typical frequency range for LS chips. They max out at about 25MHz. You could use a schmitt trigger in front of the counter to see if the sin wave is causing problems but I expect a frequency limitation. Try increasing the vcc to about 5.5 volts.
     
    Last edited: Jul 19, 2008
  3. KB1LQC

    KB1LQC Guest

    Wow haha, I knew I was missing something, didn't occur to me to check the maximum frequency of the chip! I guess thats what I get for selective reading of the data sheet :DMaybe I will check what I built with an oscillator around 10 MHz, just to see if its working but it looks like I will be buying some different D Flip-Flops.
     
  4. WA9SVD

    WA9SVD Ham Member QRZ Page

    Remember, there will also be a difference in power consumption, and mixing LS and HCT logic (even within max "speed" limits) can cause loading problem, particularly if you try driving multiple LSTTL devices from a single HCT (or other CMOS TTL) output. the noise margins are also different in most cases.
     
  5. AC0FP

    AC0FP Ham Member QRZ Page

    Its been along time since I've done this but I think I had to use 74S74's to get some speed out of that type of setup.

    Try going down in frequency to see if you can get your present setup to work as a check of your hookup.

    73,

    Frank
     
  6. G4ALA

    G4ALA Ham Member QRZ Page

    Tie 'em High

    Faced with the same problem, and eventually realizing that the set/reset terminals might flap about indeterminately at CMOS impedance levels, I eventually tied the set and rest terminals high. Voila! Total functionality ensued. While it does not seem from the spec that attachment of the set/reset terminals is required, it does seem to be necessary.

    Try this fix. You might be surprised.

    Good Luck.

    73

    John

    G4ALA
     
  7. K8ERV

    K8ERV Ham Member QRZ Page

    My frequency got divided when I hit 60---

    TOM K8ERV Montrose Colo
     
  8. AC0FP

    AC0FP Ham Member QRZ Page

    Sorry to hear that! I think they have some pills now that will help! :D:D
     
  9. K9STH

    K9STH Ham Member QRZ Page

    When my wife hit "40" I said that I was going to trade her in for a couple of 20 year-olds. At the time I had a Baptist "preacher" working for me. He looked me straight in the eye and said, "you're not wired for 220"! He was also a licensed amateur radio operator.

    Glen, K9STH
     
  10. KL7AJ

    KL7AJ Ham Member QRZ Page

    You might also want to try some ECL logic devices. (
    Been so long, I forgot the "family" prefix for these) Plessey used to be the big player in ECL "back in the day".
    Don't know who makes it now.

    eric
     
  11. AC0OB

    AC0OB Ham Member QRZ Page

    Freq Divider

    It is always a good idea to pull-up the SETS and Clears not being used and ground any unused pins not outputs.

    For the 74LS74, the MAX clock frequency is around 32 Mhz so you're pushing it with that logic family.

    For the 74HC/HCT74, the MAX clock frequency is around 70 Mhz@5.0V so that is why 28 MhZ would work fine for this logic family.

    For the74LS74, I would pull pins 1/13 up to 5V through a 4.7K with a 0.01 uF cap to ground. This will Reset/Clear the FF on power up. (A poor man's PUR).

    While most clock inputs do have Schmitt trigger devices internal, I would square the clock up with a saturated NPN transistor or Schmitt trigger, as has been previously suggested.
     
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